Split gate non-volatile flash memory cells are well known. An exemplary non-volatile split gate memory cell is shown in FIG. 33. The memory cell comprises a semiconductor substrate 10 of a first conductivity type, such as P type. The substrate has a surface on which there is formed a first region 17 (also known as the source line SL) of a second conductivity type, such as N type. A second region 18 (also known as the drain line) also of N type is formed on the surface of the substrate. Between the first region and the second region is a channel region 22. A bit line BL 20 is connected to the second region 18. A word line WL 26 is positioned above a first portion of the channel region 22 and is insulated therefrom. The word line 26 has little or no overlap with the second region 18. A floating gate FG 12 is over another portion of the channel region 22. The floating gate 12 is insulated therefrom, and is adjacent to the word line 26. The floating gate 12 is also adjacent to the first region 17. The floating gate 12 may overlap the first region 17 to provide coupling from the region into the floating gate 12. A coupling gate CG 14 (also known as control gate) is over the floating gate 12 and is insulated therefrom. An erase gate EG 16 is over the first region 17 and is adjacent to the floating gate 12 and the coupling gate 14 and is insulated therefrom. The top corner of the floating gate 12 may point toward the inside corner of the T-shaped erase gate 16 to enhance erase efficiency. The erase gate 16 is also insulated from the first region 17. The cell is more particularly described in U.S. Pat. No. 7,868,375 whose disclosure is incorporated herein by reference in its entirety.
One exemplary operation for erase and program of the non-volatile memory cell is as follows. The cell is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate 16 with other terminals equal to zero volt. Electrons tunnel from the floating gate 12 into the erase gate 16 causing the floating gate 12 to be positively charged, turning on the cell in a read condition. The resulting cell erased state is known as ‘1’ state. The cell is programmed, through a source side hot electron programming mechanism, by applying a high voltage on the coupling gate 14, a high voltage on the source line 17, a medium voltage on the erase gate 16, and a programming current on the bit line 20. A portion of electrons flowing across the gap between the word line 26 and the floating gate 12 acquire enough energy to inject into the floating gate 12 causing the floating gate 12 to be negatively charged, turning off the cell in read condition. The resulting cell programmed state is known as ‘0’ state.
One set of exemplary operating parameters for the memory cell of FIG. 33 is shown in FIG. 34.
Another set of exemplary operating parameters for the memory cell of FIG. 33 is shown in FIG. 35.
Another set of exemplary operating parameters for the memory cell of FIG. 33 is shown in FIG. 36.
An exemplary layout for a flash memory system comprising memory cells of the type shown in FIG. 33 is shown in FIG. 37.
In prior art systems, memory cells typically are formed in pairs that share certain components. For example, U.S. Pat. No. 6,747,310 discloses such memory cells having source and drain regions defining a channel region there between, a select gate over one portion of the channel regions, a floating gate over the other portion of the channel region, and an erase gate over the source region. The memory cells are formed in pairs that share a common source region and common erase gate, with each memory cell having its own channel region in the substrate extending between the source and drain regions (i.e. there are two separate channel regions for each pair of memory cells). The lines connecting all the control gates for memory cells in a given column run vertically. The same is true for the lines connecting the erase gates and the select gates, and the source lines. The bit lines connecting drain regions for each row of memory cells run horizontally.
FIG. 1 illustrates a first such memory cell design (CELL #1), where each memory cell includes a floating gate 12 (FG) disposed over and insulated from the substrate 10, a control gate 14 (CG) disposed over and insulated from the floating gate 12, an erase gate 16 (EG) disposed adjacent to and insulated from the floating and control gates 12/14 and disposed over and insulated from the substrate 10, where the erase gate is created with a T shape such that a top corner of the control gate CG faces the inside corner of the T shaped erase gate to improve erase efficiency, and a drain region 18 (DR) in the substrate adjacent the floating gate 12 (with a bit line contact 20 (BL) connected to the drain diffusion regions 18 (DR)). The memory cells are formed as pairs of memory cells (A on the left and B on the right), sharing a common erase gate 16. This cell design differs from that in the '310 patent discussed above at least in that it lacks a source region under the erase gate EG, lacks a select gate (also referred to as a word line), and lacks a channel region for each memory cell. Instead, a single continuous channel region 22 extends under both memory cells (i.e. extends from the drain region 18 of one memory cell to the drain region 18 of the other memory cell). To read or program one memory cell, the control gate 14 of the other memory cell is raised to a sufficient voltage to turn on the underlying channel region portion via voltage coupling to the floating gate 12 there between (e.g. to read or program cell A, the voltage on FGB is raised via voltage coupling from CGB to turn on the channel region portion under FGB).
FIG. 2 illustrates a second such memory cell design (CELL #2), which is the same as CELL #1 except there are no bit line contacts 20 in electrical contact with the drain regions 18 (DR), and instead there is an erase gate line 24 (EGL) that connects together all the erase gates 16 (EG) in the row of memory cells.
FIG. 3 illustrates a third such memory cell design (CELL #3), where each memory cell includes a floating gate 12 (FG) disposed over and insulated from the substrate and a control gate 14 (CG) disposed over and insulated from the floating gate 12. To one side of the floating and control gates 12/14 is a word line (select) gate 26 (WL), and to the other side of the floating and control gates 12/14 is an erase gate 16 (EG). A drain region 18 (DR) is disposed in the substrate 10 underneath the erase gate 16 (EG). The memory cells are formed as pairs of memory cells sharing a common word line gate 26, and with a single continuous channel region 22 extending under both memory cells (i.e. extends from the drain region 18 of one memory cell to the drain region 18 of the other memory cell 18). As with Cells #1 and #2, to read or program one memory cell, the control gate 14 of the other memory cell is raised to a sufficient voltage to turn on the underlying channel region portion via voltage coupling to the floating gate 12 there between.
Due to the close proximity of components in CELLS #1, #2, and #3, one drawback is that programming errors often occur. For example, when a programming current is applied to a first bitline to program a selected memory cell coupled to that first bitline, a cell attached to the second bitline might inadvertently be programmed as well. What is needed is a mechanism for inhibiting the programming of cells attached to all bitlines except for the bitline attached to the selected cell.